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august 2010 doc id 15251 rev 5 1/77 77 STA339BW 2.1-channel high-effici ency digital audio system features ? wide voltage supply range ? 5 v to 26 v (operating range) ? 30 v (absolute maximum rating) ? 3 power output configurations ? 2 channels of ternary pwm (stereo mode) (2 x 20 w into 8 ? at 18 v) ? 3 channels - left, right using binary and lfe using ternary pwm (2.1 mode) (2 x 9 w + 1x20w into 2x4 ? , 1 x 8 ? at 18 v) ? 2 channels of ternary pwm (2 x 20 w) + stereo lineout ternary ? 2.1 channels of 24-bit ffx ? 100 db snr and dynamic range ? selectable 32 to 192 khz input sample rates ? i 2 c control with selectable device address ? digital gain/attenuation +48 db to -80 db with 0.5 db/step resolution ? soft volume update with programmable ratio ? individual channel and master gain/attenuation ? two independent drc configurable as a dual-band anti-clipper (b 2 drc) or as independent limiters/compressors ? eq-drc for drc based on filtered signals ? dedicated lfe processing for bass boosting with 0.5 db/step resolution ? audio presets: ? 15 preset crossover filters ? 5 preset anti-clipping modes ? preset night-time listening mode ? individual channel and master soft/hard mute ? independent channel volume and dsp bypass ? automatic zero-detect mute ? automatic invalid input-detect mute ? 2-channel i 2 s input data interface ? input and output channel mapping ? up to 8 user-programmable biquads per channel with 28-bit resolution ? 3 coefficient banks for eq presets storing with fast recall via i 2 c interface ? bass/treble tones and de-emphasis control ? selectable high-pass filter for dc blocking ? advanced am interference frequency switching and noise suppression modes ? selectable high- or low-bandwidth noise-shaping topologies ? variable max power correction for lower full-power thd ? selectable clock input ratio ? 96 khz internal processing sample rate, 24 to 28-bit precision ? thermal overload and short-circuit protection embedded ? video apps: 576 * f s input mode supported ? fully compatible with STA339BWs. powersso-36 (slug down) table 1. device summary order code package packaging STA339BW powersso-36 slug down tube STA339BWtr powersso-36 slug down tape and reel www.st.com
contents STA339BW 2/77 doc id 15251 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15 3.5 electrical specifications for the power sectio n . . . . . . . . . . . . . . . . . . . . . 16 3.6 power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7.1 functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5i 2 c bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.1 current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.2 current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.3 random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STA339BW contents doc id 15251 rev 5 3/77 5.4.4 random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.5 write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.6 read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 configuration register a (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1 master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.2 interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.3 thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.4 thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.5 fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 configuration register b (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.2 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.3 serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.4 delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.5 channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 configuration register c (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.1 ffx power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.2 ffx compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3.3 overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . 34 6.4 configuration register d (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.1 high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.2 de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.3 dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4.4 post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.5 biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.6 dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 35 6.4.7 zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.8 submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 configuration register e (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.1 max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.2 max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.3 noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5.4 am mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5.5 pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5.6 distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 37
contents STA339BW 4/77 doc id 15251 rev 5 6.5.7 zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5.8 soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6 configuration register f (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.1 output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6.2 invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.3 binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.4 lrck double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.5 auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.6 ic power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6.7 external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7 volume control registers (addr 0x06 - 0x0a) . . . . . . . . . . . . . . . . . . . . . . 45 6.7.1 mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7.2 master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7.3 channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7.4 channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7.5 channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.8 audio preset registers (addr 0x0b and 0x0c) . . . . . . . . . . . . . . . . . . . . . 47 6.8.1 audio preset register 1 (addr 0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.8.2 audio preset register 2 (addr 0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.8.3 am interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.8.4 bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.9 channel configuration registers (addr 0x0e - 0x10) . . . . . . . . . . . . . . . . . 49 6.9.1 tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.9.2 eq bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.9.3 volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.9.4 binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.9.5 limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.9.6 output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.10 tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.10.1 tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.11 dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 51 6.11.1 limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.11.2 limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.11.3 limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.11.4 limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.11.5 limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 55
STA339BW contents doc id 15251 rev 5 5/77 6.11.6 limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 55 6.11.7 limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 56 6.11.8 limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 56 6.12 user-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 56 6.12.1 coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.12.2 coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.12.3 coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.12.4 coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.12.5 coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.6 coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.7 coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.8 coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.9 coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.10 coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.11 coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.12.12 coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.13 coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.14 coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.15 coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.16 coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.17 coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.12.18 user-defined eq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.12.19 prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.12.20 postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.12.21 overcurrent postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.13 variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 63 6.14 variable distortion compensation registers (addr 0x29 - 0x2a) . . . . . . . . 63 6.15 fault detect recovery constant registers (addr 0x2b - 0x2c) . . . . . . . . . . 64 6.16 device status register (addr 0x2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.17 eq coefficients and drc configuration register (addr 0x31) . . . . . . . . . . 65 6.18 extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 65 6.18.1 dual-band drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.18.2 eq drc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.18.3 extended post scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.18.4 extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.18.5 extended biquad selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
contents STA339BW 6/77 doc id 15251 rev 5 6.19 eq soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 69 6.20 drc rms filter coefficients (addr 0x39 - 0x3e) . . . . . . . . . . . . . . . . . . . . 70 7 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1 application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
STA339BW list of figures doc id 15251 rev 5 7/77 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. pin connection powersso-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 5. test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. left and right processing part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. processing part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. ocfg = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 12. ocfg = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. ocfg = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 14. ocfg = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 15. output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. 2.0 channels (ocfg = 00) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17. 2.1 channels (ocfg = 01) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18. 2.1 channels (ocfg = 10) pwm slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. b 2 drc scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 21. eqdrc scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 22. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23. output configuration for stereo btl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 24. double-layer pcb with 2 copper ground areas and 16 via holes . . . . . . . . . . . . . . . . . . . 73 figure 25. powersso-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 26. powersso-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
list of tables STA339BW 8/77 doc id 15251 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. ir bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 15. thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17. serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 19. supported serial audio input formats for msb-first (saifb = 0) . . . . . . . . . . . . . . . . . . . . . 30 table 20. supported serial audio input formats for lsb-first (saifb = 1) . . . . . . . . . . . . . . . . . . . . . 31 table 21. delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 22. channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. ffx power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 24. output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 25. ffx compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 26. compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 27. overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 28. high-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 29. de-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30. dsp bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 31. post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 32. biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 33. dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 34. zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 35. submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 36. max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 37. max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 38. noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 39. am mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 40. pwm speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 41. distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 42. zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 43. soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 44. output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 45. output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 46. invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 47. binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 48. lrck double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
STA339BW list of tables doc id 15251 rev 5 9/77 table 49. auto eapd on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 50. ic power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 51. external amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 52. line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 53. master volume offset as a function of mv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 54. channel volume as a function of cxv[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 55. audio preset gain compression/limiters selection for amgc[3:2] = 00. . . . . . . . . . . . . . . . 47 table 56. am interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 57. audio preset am switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 58. bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 59. bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 60. tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 61. eq bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 62. binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 63. channel limiter mapping as a function of cxls bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 64. channel output mapping as a function of cxom bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 65. tone control boost/cut as a function of btc and ttc bits . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 66. limiter attack rate as a function of lxa bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 67. limiter release rate as a function of lxr bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 68. limiter attack threshold as a function of lxat bits (ac mode) . . . . . . . . . . . . . . . . . . . . . . 54 table 69. limiter release threshold as a function of lxrt bits (ac mode). . . . . . . . . . . . . . . . . . . . . 54 table 70. limiter attack threshold as a function of lxat bits (drc mode) . . . . . . . . . . . . . . . . . . . . 55 table 71. limiter release threshold as a as a function of lxrt bits (drc mode) . . . . . . . . . . . . . . . 55 table 72. ram block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 62 table 73. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 74. eq ram select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 75. anti-clipping and drc preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 76. anti-clipping selection for amgc[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 77. post scale setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 78. extended attack rate setup for limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 79. extended attack rate setup for limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 80. de-emphasis filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 81. bass filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 82. treble filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 83. soft volume (increasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 84. soft volume (decreasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 85. powersso-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 86. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
description STA339BW 10/77 doc id 15251 rev 5 1 description the STA339BW is an integrated solution of digital audio processing, digital amplifier control, and ffx-power output stage, thereby creating a high-power single-chip ffx ? solution comprising high-quality, high-efficiency, all digital amplification. STA339BW is based on ffx (fully flexible amp lification) processor, a stmicroelectronics proprietary technology. ffx is the evolution and the enlargement of the st ternary technology: the new processor can be configured to work in ternary, binary, binary differential and phase shift pwm modulation schemes. STA339BW contains the ternary, binary and binary differential implementations, a subset of the full capability of the ffx processor. the STA339BW is part of the sound terminal? family that provides full digital audio streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment. the STA339BW power section consists of four independent half bridges. these can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half bridges and a single full bridge, providing up to 2 x 9 w + 1 x 20 w of power output. two channels can be provided by two full bridges, providing up to 2 x 20 w of power. the ic can also be configured as 2.1 channels with 2 x 20 w provided by the device and external power for ffx power drive. also provided in the STA339BW are a full assortment of digital processing features. this includes up to 8 programmable 28-bit biquads (eq) per channel and bass/treble tone control. available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions. this includes audio preset volume loudness, preset volume curves and preset eq settings. there are also new advanced am radio interference reduction modes. dual band drc dynamically equalizes the system to provide sp eaker linear frequency response regardless output power level. this feature independen tly processes the two bands, controlling, dyna mically, the output power level in each band and so providing a better sound quality. the serial audio data input interface accepts all possible formats, including the popular i 2 s format. three channels of ffx processing are provided. this high-quality conversion from pcm audio to ffx pwm switching waveform provides over 100 db snr and dynamic range.
STA339BW description doc id 15251 rev 5 11/77 1.1 block diagram figure 1. block diagram protection current/thermal logic regulators bias power control ffx pll volume control channel 1a channel 1b channel 2a channel 2b i 2 s interface power digital dsp i 2 c
pin connections STA339BW 12/77 doc id 15251 rev 5 2 pin connections 2.1 connection diagram figure 2. pin connection powersso-36 (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vdd_dig gnd_dig scl sda int_line reset sdi lrcki bicki xti gnd_pll filter_pll vdd_pll pwrdn gnd_dig vdd_dig twarn / out4a eapd / out4b gnd_sub sa test_mode vss vcc_reg out2b gnd2 vcc2 out2a out1b vcc1 gnd1 out1a gnd_reg vdd config out3b / ffx3b out3a / ffx3a d05au1638 table 2. pin description pin type name description 1 gnd gnd_sub substrate ground 2i sa i 2 c select address (pull-down) 3 i test_mode this pin must be connected to ground (pull-down) 4 i/o vss internal reference at v cc - 3.3 v 5 i/o vcc_reg internal v cc reference 6 o out2b output half bridge 2b 7 gnd gnd2 power negative supply 8 power vcc2 power positive supply 9 o out2a output half bridge 2a 10 o out1b output half bridge 1b
STA339BW pin connections doc id 15251 rev 5 13/77 11 power vcc1 power positive supply 12 gnd gnd1 power negative supply 13 o out1a output half bridge 1a 14 gnd gnd_reg internal ground reference 15 power vdd internal 3.3 v reference voltage 16 i config paralleled mode command 17 o out3b / ffx3b pwm out ch3b / external bridge driver 18 o out3a / ffx3a pwm out ch3a / external bridge driver 19 o eapd / out4b power down for external bridge / pwm out ch4b 20 i/o twarn / out4a thermal warning from external bridge (pull-up when input) / pwm out ch4a 21 power vdd_dig digital supply voltage 22 gnd gnd_dig digital ground 23 i pwrdn power down (pull-up) 24 power vdd_pll positive supply for pll 25 i filter_pll connection to pll filter 26 gnd gnd_pll negative supply for pll 27 i xti pll input clock 28 i bicki i 2 s serial clock 29 i lrcki i 2 s left/right clock 30 i sdi i 2 s serial data channels 1 and 2 31 i reset reset (pull-up) 32 o int_line fault interrupt 33 i/o sda i 2 c serial data 34 i scl i 2 c serial clock 35 gnd gnd_dig digital ground 36 power vdd_dig digital supply voltage table 2. pin description (continued) pin type name description
electrical specifications STA339BW 14/77 doc id 15251 rev 5 3 electrical specifications 3.1 absolute maximum ratings warning: stresses beyond those listed in table 3 above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). in this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. 3.2 thermal data table 3. absolute maximum ratings symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) -0.3 - 30 v vdd_dig digital supply voltage -0.3 - 4 v vdd_pll pll supply voltage -0.3 - 4 v t op operating junction temperature -20 - 150 c t stg storage temperature -40 - 150 c table 4. thermal data parameter min typ max unit r th j-case thermal resistance junction-case (thermal pad) - - 1.5 c/w r th j-amb thermal resistance junction-ambient (1) 1. see section 8: package thermal characteristics on page 73 for details. ---c/w t th-sdj thermal shut-down junction temperature - 150 - c t th-w thermal warning temperature - 130 - c t th-sdh thermal shut-down hysteresis - 20 - c
STA339BW electrical specifications doc id 15251 rev 5 15/77 3.3 recommended operating conditions 3.4 electrical specifications for the digital section table 5. recommended operating condition symbol parameter min typ max unit v cc power supply voltage (vccxa, vccxb) 5 - 26 v vdd_dig digital supply voltage 2.7 3.3 3.6 v vdd_pll pll supply voltage 2.7 3.3 3.6 v t amb ambient temperature -20 - 70 c table 6. electrical specifications - digital section symbol parameter conditions min typ max unit i il low-level input current without pull-up/down device vi = 0 v -10 1 10 a i ih high-level input current without pull-up/down device vi = vdd_dig = 3.6 v -10 1 10 a v il low-level input voltage - - - 0.2 * vdd_dig v v ih high-level input voltage - 0.8 * vdd_dig --v v ol low-level output voltage iol = 2 ma - - 0.4 * vdd_dig v v oh high-level output voltage ioh = 2 ma 0.8 * vdd_dig --v i pu pull-up/down current - 25 66 125 a r pu equivalent pull-up/down resistance --50-k ?
electrical specifications STA339BW 16/77 doc id 15251 rev 5 3.5 electrical specificatio ns for the power section the specifications given in this section are valid for the operating conditions: v cc =18v, f=1khz, f sw = 384 khz, t amb = 25 c and r l = 8 ? , unless otherwise specified. table 7. electrical specifications - power section symbol parameter conditions min typ max unit po output power btl thd = 1% - 16 - w thd = 10% - 20 - output power se thd = 1% - 4 - w thd = 10% - 5 - r dson power pchannel/nchannel mosfet (total bridge) l d = 1.5 a - 180 250 m ? gp power pchannel rdson matching l d = 1.5 a 95 - - % gn power nchannel rdson matching l d = 1.5 a 95 - - % idss power pchannel/nchannel leakage v cc = 20 v - - 10 a i ldt low current dead time (static) resistive load (1) - 8 15 ns i hdt high current dead time (dynamic) i load = 1.5 a (1) - 15 30 ns t r rise time resistive load (1) - 10 18 ns t f fall time resistive load (1) - 10 18 ns v cc supply voltage operating voltage - 5 - 26 v i vcc supply current from v cc in power down pwrdn = 0 - 0.1 1 ma supply current from v cc in operation pcm input signal = - 60 dbfs, switching frequency = 384 khz, no lc filters - 52 60 ma i vdd supply current ffx processing (reference only) internal clock = 49.152 mhz -5570ma i lim overcurrent limit (2) 3.03.84.0a i sc short circuit protection hi-z output 3.8 4.8 - a uvl undervoltage protection - - 3.5 4.3 v t min output minimum pulse width no load 20 30 60 ns dr dynamic range - - 100 - db snr signal to noise ratio, ternary mode a-weighted - 100 - db signal to noise ratio binary mode - - 90 - db pssr power supply rejection ratio ffx stereo mode, <5 khz v ripple = 1 v rms audio input = dither only -80-db
STA339BW electrical specifications doc id 15251 rev 5 17/77 thd+n total harmonic distortion + noise ffx stereo mode, po = 1 w f=1khz -0.2-% x ta l k crosstalk ffx stereo mode, <5 khz one channel driven at 1 w other channel measured -80-db peak efficiency, ffx mode po = 2 x 20 w into 8 ? -90- % peak efficiency,binary modes po = 2 x 9 w into 4 ? + 1 x 20 w into 8 ? -87- 1. refer to figure 5: test circuit 1 . 2. limit current if the register (ocrb par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. when disabled refer to the isc. table 7. electrical specifications - power section (continued) symbol parameter conditions min typ max unit
electrical specifications STA339BW 18/77 doc id 15251 rev 5 3.6 power on/off sequence figure 3. power-on sequence note: the definition of a stable clock is when f max - f min < 1 mhz. section 6.2.3 on page 30 gives information on setting up the i 2 s interface. figure 4. power-off sequence for pop-free turn-off don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care don?t care cmd0 cmd1 cmd2 vcc vdd_dig xti reset i 2 c pwdn tr tc don?t care note: no specific vcc and vdd_dig turn ? on sequence is required tr = minimum time between xti master clock stable and reset removal: 1 ms tc = minimum time between reset removal and i 2 c program, sequence start: 1ms don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care don?t care vcc vdd_dig xti don?t care soft mute reg. 0x07 data 0xfe soft eapd reg. 0x05 bit 7 = 0 don?t care fe don?t care don?t care note: no specific vcc and vdd_dig turn ? off sequence is required
STA339BW electrical specifications doc id 15251 rev 5 19/77 3.7 testing 3.7.1 functional pin definition figure 5. test circuit 1 figure 6. test circuit 2 table 8. functional pin definition pin name number logic value ic status pwrdn 23 0 low consumption 1 normal operation twarn 20 0 a temperature warning is indicated by the external power stage 1 normal operation eapd 19 0 low consumption for power stage all internal regulators are switched off 1 normal operation dtr dtf vcc (3/4)vcc (1/2)vcc (1/4)vcc t outxy low current dead time = max(dtr, dtf) +vcc duty cycle = 50% inxy outxy gnd vdc = vcc/2 rload = 8 ? + - high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload = 4 ? q2 outxb dtout(b) dtin(b) dtout(a) 470nf 470nf 470nf iout iout q4 q1 q3 inxb d06au1651_00 inxa dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of iout in the direction shown in figure 10 10 outxa
processing data paths STA339BW 20/77 doc id 15251 rev 5 4 processing data paths the whole processing chain is composed of two consecutive sections. in the first one dual-channel processing is implemented, as desc ribed below. then each channel is fed into the post-mixing block where there is a choice of processing, either the dual-band drc is disabled or it is enabled. when b 2 drc is disabled a third channel, typically used in 2.1 output configuration and with cross-over filters enabled, is used. when b 2 drc is enabled the 2.0 output configuration with cross-over filters for defining the cutoff frequency of the two bands is used. the first section, figure 7 , begins with a 2x oversampling fi r filter allowing a 2 * fs audio processing. then a selectable high-pass filter removes the dc level (enabled if hfb = 0). the channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration (bits bql, bq5, bq6, bq7 and xo[3:0]). by default, four independent filters per channel are enabled, plus the preconfigured de- emphasis, bass and treble controls (bql = 0, bq5 = 0, bq6 = 0, bq7 = 0). if the coefficient sets are linked (bql = 1) then it is possible to use the de-emphasis, bass and treble filter in a user defined configuration (provided the relevant bqx bits are set to 1). in other words both channels use the same processing coefficients and can have up to 7 filters each. note that if bql = 0 the bqx bits are ignored and the 5th, 6th and 7th filters are configured as de-emphasis, bass and treble controls, respectively. moreover the common 8th filter, from the subsequent processing section, can be available on both channels (provided the pre-defined cross-over frequencies are not used, xo[3:0] = 0, and the dual-band drc is not used). in the second section, mixing and crossover filters are available. if b 2 drc is not enabled (lower schematic in figure 8 ) they are fully user-programmable and allow a third channel (2.1 outputs) to be generated. alternatively, in b 2 drc mode (upper schematic in figure 8 ), those blocks will be used to split the sub-band and define the cutoff frequencies of the two bands. a prescaler and a final post scaler allow full control over the signal dynamics before and after, respectively, the filtering stages. a mixer function is also available. figure 7. left and right processing part 1 from i 2 s input interface prescale pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user-defined filters if dspb=0 and c1eqbp=0 x2 fir over l sampling frequency = fs sampling frequency = 2 * fs pre-scale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling l bass treble if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user-defined filters if dspb=0 and c2eqbp=0 x2 fir over l pre-scale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling r bass treble if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 from i 2 s input interface prescale pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user-defined filters if dspb=0 and c1eqbp=0 x2 fir over l sampling frequency = fs sampling frequency = 2 * fs pre-scale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling l bass treble if c1tcb=0 btc: bass boost/cut ttc: treble boost/cut prescale pass filter biquad #1 biquad #2 biquad #3 biquad #4 if hpb=0 user-defined filters if dspb=0 and c2eqbp=0 x2 fir over l pre-scale hi-pass filter biquad #1 biquad #2 biquad #3 biquad #4 de-emph. if demp=0 x2 fir over sampling r bass treble if c2tcb=0 btc: bass boost/cut ttc: treble boost/cut if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7 if bq5=1 and bql=1 biquad #5 if bq6=1 and bql=1 biquad #6 if bq7=1 and bql=1 biquad #7
STA339BW processing data paths doc id 15251 rev 5 21/77 figure 8. processing part 2 crossover frequency determined by xo setting user defined if xo = 0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 channel 1/2 biquad #5 -------------- hi-pass xo filter volume and limiter volume and limiter volume and limiter post-scale post-scale post-scale channel 1/2 biquad #5 -------------- hi-pass xo filter channel 3 biquad -------------- low-pass xo filter b 2 drc disabled crossover frequency determined by xo setting user defined if xo = 0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter lo-pass xo filter user-defined mix coefficients vol and limiter vol and limiter vol and limiter post scale post scale post scale r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 channel 1/2 biquad #5 -------------- hi-pass xo filter volume and limiter volume and limiter volume and limiter post-scale post-scale post-scale channel 1/2 biquad #5 -------------- hi-pass xo filter channel 3 biquad -------------- low-pass xo filter b 2 drc disabled dual-band drc disabled crossover frequency determined by xo setting user-defined if xo = 0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter user-defined mix coefficients post scale post scale r l + + + c1mx2 = 0x00000 c2mx1= 0x000000 c2mx2 = 0x7fffff c3mx1 = 0x40000 c3mx2 = 0x400000 c1mx1 = 0x7fffff b 2 drc hi-pass filter post-scale post-scale vol and limiter drc1 drc1 drc2 ch1 volume ch2 volume ch3 volume b 2 drc hi-pass filter + + b 2 drc enabled drc2 ch3 volume - + - + crossover frequency determined by xo setting user-defined if xo = 0000 r l + + + c1mx2 c2mx1 c2mx2 c3mx1 c3mx2 c1mx1 hi-pass xo filter hi-pass xo filter user-defined mix coefficients post scale post scale r l + + + c1mx2 = 0x00000 c2mx1= 0x000000 c2mx2 = 0x7fffff c3mx1 = 0x40000 c3mx2 = 0x400000 c1mx1 = 0x7fffff b 2 drc hi-pass filter post-scale post-scale vol and limiter drc1 drc1 drc2 ch1 volume ch2 volume ch3 volume b 2 drc hi-pass filter + + b 2 drc enabled drc2 ch3 volume - + - + - + - + dual-band drc enabled
i 2 c bus specification STA339BW 22/77 doc id 15251 rev 5 5 i 2 c bus specification the STA339BW supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA339BW is always a slave device in all of its communications. it can operate at up to 400 kb/s (fast-mode bit rate). the STA339BW i 2 c interface is a slave only interface. 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA339BW and the bus master. 5.1.4 data input during the data input the STA339BW samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the STA339BW, the master must initiate with a start condition. following this, the master sends onto the sda line 8-bits (msb first) corresponding to the device select address and read or write mode. the seven most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA339BW the i 2 c interface has two device addresses depending on the sa port configuration, 0x38 when sa = 0, and 0x3a when sa = 1. the eighth bit (lsb) identifies read or write operation rw, this bit is set to 1 in read mode and to 0 for write mode. after a start condition the STA339BW identifies on the bus the device address and if a match is found, acknowledges the identification on the sda bus during the 9th bit time. the byte following the device identification byte is the internal space address.
STA339BW i 2 c bus specification doc id 15251 rev 5 23/77 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA339BW acknowledges this and the writes for the byte of internal address. after receiving the internal byte address the STA339BW again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, this is acknowledged by the STA339BW. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. 5.4 read operation 5.4.1 current address byte read following the start condition the master sends a device select code with the rw bit set to 1. the STA339BW acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 5.4.2 current address multi-byte read the multi-byte read modes can start from any internal address. sequential data bytes are read from sequential addresses within the STA339BW. the master acknowledges each data byte read and then generates a stop condition terminating the transfer. 5.4.3 random ad dress byte read following the start condition the master sends a device select code with the rw bit set to 0. the STA339BW acknowledges this and then the master writes the internal address byte. after receiving, the internal byte ad dress the STA339BW again responds with an acknowledgement. the master then initiates another start condition and sends the device select code with the rw bit set to 1. the STA339BW acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. 5.4.4 random address multi-byte read the multi-byte read modes could start from any internal address. sequential data bytes are read from sequential addresses within the STA339BW. the master acknowledges each data byte read and then generates a stop condition terminating the transfer.
i 2 c bus specification STA339BW 24/77 doc id 15251 rev 5 5.4.5 write mode sequence figure 9. write mode sequence 5.4.6 read mode sequence figure 10. read mode sequence dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no a ck start rw dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data a ck start rw data a ck no a ck stop data rw= high
STA339BW register description doc id 15251 rev 5 25/77 6 register description table 9. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 0x00 confa fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb c2im c1im dscke saifb sai3 sai2 sai1 sai0 0x02 confc ocrb reserved csz3 csz2 csz1 csz0 om1 om0 0x03 confd sme zde drc bql psl dspb demp hpb 0x04 confe sve zce dccv pwms ame nsbw mpc mpcv 0x05 conff eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 0x06 mute/loc loc1 loc0 reserved c3m c2m c1m mmute 0x07 mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x08 c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x09 c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0a c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0b auto1 reserved amgc1 amgc0 reserved 0x0c auto2 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 0x0d auto3 reserved 0x0e c1cfg c1om1 c1om0 c1ls1 c1ls0 c1bo c1vbp c1eqbp c1tcb 0x0f c2cfg c2om1 c2om0 c2ls1 c2ls0 c2bo c2vbp c2eqbp c2tcb 0x10 c3cfg c3om1 c3om0 c3ls1 c3ls0 c3bo c3vbp reserved 0x11 tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 0x12 l1ar l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 0x13 l1atrt l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 0x14 l2ar l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 0x15 l2atrt l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 0x16 cfaddr reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x17 b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x18 b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x19 b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x1a b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x1b b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x1c b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x1d a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 0x1e a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x1f a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0
register description STA339BW 26/77 doc id 15251 rev 5 0x20 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x21 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x22 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x23 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x24 b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x25 b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x26 cfud reserved ra r1 wa w1 0x27 mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x28 mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x29 dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x2a dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x2b fdrc1 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 0x2c fdrc2 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 0x2d status pllul fault uvfault ovfault ocfault ocwarn tfault twarn 0x2e reserved reserved ro1bact r5bact r4bact r3bact r2bact r1bact 0x2f reserved reserved r01bend r5bend r4bend r3bend r2bend r1bend 0x30 reserved reserved r5bbad r4bbad r3bbad r2bbad r1bbad 0x31 eqcfg xob reserved amgc3 amgc2 reserved sel1 sel0 0x32 eath1 e at h e n 1 e at h 1 [ 6 ] e at h 1 [ 5 ] e at h 1 [ 4 ] e at h 1 [ 3 ] e at h 1 [ 2 ] e at h 1 [ 1 ] e at h 1 [ 0 ] 0x33 erth1 erthen1 erth1[6] erth1[5] erth1[4] erth1[3] erth1[2] erth1[1] erth1[0] 0x34 eath2 e at h e n 2 e at h 2 [ 6 ] e at h 2 [ 5 ] e at h 2 [ 4 ] e at h 2 [ 3 ] e at h 2 [ 2 ] e at h 2 [ 1 ] e at h 2 [ 0 ] 0x35 erth2 erthen2 erth2[6] erth2[5] erth2[4] erth2[3] erth2[2] erth2[1] erth2[0] 0x36 confx mdrc[1] mdrc[0] ps48db xar1 xar2 bq5 bq6 bq7 0x37 svca reserved svupe svup[4] svup[3] svup[2] svup[1] svup[0] 0x38 svcb reserved svdwe svdw[4] svdw[3] svdw[2] svdw[1] svdw[0] 0x39 rms0a r_c0[23] r_c0[22] r_c0[21] r_c0[20] r_c0[19] r_c0[18] r_c0[17] r_c0[16] 0x3a rms0b r_c0[15] r_c0[14] r_c0[13] r_c0[12] r_c0[11] r_c0[10] r_c0[9] r_c0[8] 0x3b rms0c r_c0[7] r_c0[6] r_c0[5] r_c0[4] r_c0[3] r_c0[2] r_c0[1] r_c0[0] 0x3c rms1a r_c1[23] r_c1[22] r_c1[21] r_c1[20] r_c1[19] r_c1[18] r_c1[17] r_c1[16] 0x3d rms1b r_c1[15] r_c1[14] r_c1[13] r_c1[12] r_c1[11] r_c1[10] r_c1[9] r_c1[8] 0x3e rms1c r_c1[7] r_c1[6] r_c1[5] r_c1[4] r_c1[3] r_c1[2] r_c1[1] r_c1[0] table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
STA339BW register description doc id 15251 rev 5 27/77 6.1 configuration register a (addr 0x00) 6.1.1 master clock select the STA339BW supports sample rates of 32 khz, 44.1 khz, 48 khz, 88.2 khz, 96 khz, 176.4 khz, and 192 khz. therefore the internal clock is: z 32.768 mhz for 32 khz z 45.1584 mhz for 44.1 khz, 88.2 khz, and 176.4 khz z 49.152 mhz for 48 khz, 96 khz, and 192 khz the external clock frequency provided to the xti pin must be a multiple of the input sample frequency (f s ). the relationship between the input clock and the input sample rate is determined by both the mcsx and the ir (input rate) register bits. the mcsx bits determine the pll factor generating the internal clock and the ir bit determines the oversampling ratio used internally. d7 d6 d5 d4 d3 d2 d1 d0 fdrb twab twrb ir1 ir0 mcs2 mcs1 mcs0 01100011 table 10. master clock select bit r/w rst name description 0r/w1 mcs0 selects the ratio between the input i 2 s sample frequency and the input clock. 1r/w1 mcs1 2r/w0 mcs2 table 11. input sampling rates input sample rate fs (khz) ir mcs[2:0] - - 101 100 011 010 001 000 32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs 88.2, 96 01 na 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs 176.4, 192 1x na 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
register description STA339BW 28/77 doc id 15251 rev 5 6.1.2 interpolation ratio select the STA339BW has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consis tent. the first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. the oversampling ratio of this interpolation is determined by the ir bits. 6.1.3 thermal warning recovery bypass if the thermal warning adjustment is enabled (twab = 0), then the thermal warning recovery determines if the -3 db output limit is removed when thermal warning is negative. if twrb = 0 and twab = 0, then when a thermal warning disappears the -3 db output limit is removed and the gain is added back to the system. if twrb = 1 and twab = 0, then when a thermal warning disappears the -3 db output limit remains until twrb is changed to zero or the device is reset. 6.1.4 thermal warning adjustment bypass the on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. input twarn is used to indicate a thermal warning table 12. internal interpolation ratio bit r/w rst name description 4:3 r/w 00 ir [1:0] selects internal interpolation ratio based on input i 2 s sample frequency table 13. ir bit settings as a function of input sample rate input sample rate fs (khz) ir 1st stage interpolation ratio 32 00 2 times oversampling 44.1 00 2 times oversampling 48 00 2 times oversampling 88.2 01 pass-through 96 01 pass-through 176.4 10 2 times downsampling 192 10 2 times downsampling table 14. thermal warning recovery bypass bit r/w rst name description 5r/w1 twrb 0: thermal warning recovery enabled 1: thermal warning recovery disabled table 15. thermal warning adjustment bypass bit r/w rst name description 6r/w1 twab 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled
STA339BW register description doc id 15251 rev 5 29/77 condition. when twarn is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 db output limit (determined by twocl in the coefficient ram) to the modulation limit in an attempt to eliminate the thermal warning condition. once the thermal warning output limit adjustment is ap plied, it remains in this state until reset, unless fdrb = 0. 6.1.5 fault detect recovery bypass the on-chip STA339BW power output block provides feedback to the digital controller using inputs to the power control block. the fault input is used to indicate a fault condition (either overcurrent or thermal). when fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (fdrc registers 0x2b- 0x2c), then toggles it back to 1. this sequenc e is repeated as log as the fault indication exists. this feature is enabled by default but can be bypassed by setting the fdrb control bit to 1. 6.2 configuration register b (addr 0x01) 6.2.1 serial audio i nput interface format table 16. fault detect recovery bypass bit r/w rst name description 7 r/w 0 fdrb 0: fault detect recovery enabled 1: fault detect recovery disabled d7 d6 d5 d4 d3 d2 d1 d0 c2im c1im dscke saifb sai3 sai2 sai1 sai0 10000000 table 17. serial audio input interface bit r/w rst name description 0r/w0 sai0 determines the interface format of the input serial digital audio interface. 1r/w0 sai1 2r/w0 sai2 3r/w0 sai3
register description STA339BW 30/77 doc id 15251 rev 5 6.2.2 serial data interface the STA339BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA339BW always acts as slave when receiving audio input from standard digital audio components. serial data for two channels is provided using three inputs: left/right clock lrcki, serial clock bicki, and serial data 1 and 2 sdi12. the sai bits (d3 to d0) and the saifb bit (d4) are used to specify the serial data format. the default serial data format is i 2 s, msb-first. available formats are shown in the tables and figure that follow. 6.2.3 serial data first bit table 18. serial data first bit saifb format 0 msb-first 1 lsb-first table 19. supported serial audio input formats for msb-first (saifb = 0) bicki sai [3:0] saifb interface format 32 * fs 0000 0 i 2 s 15-bit data 0001 0 left/right-justified 16-bit data 48 * fs 0000 0 i 2 s 16 to 23-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data 64 * fs 0000 0 i 2 s 16 to 24-bit data 0001 0 left-justified 16 to 24-bit data 0010 0 right-justified 24-bit data 0110 0 right-justified 20-bit data 1010 0 right-justified 18-bit data 1110 0 right-justified 16-bit data
STA339BW register description doc id 15251 rev 5 31/77 to make the STA339BW work properly, the serial audio interface lrcki clock must be synchronous to the pll output clock. it means that: ? the frequency of pll clock / fre quency of lrcki = n 4 cycles, where n depends on the settings in table 13 on page 28 ? the pll must be locked. if these two conditions are not met, and bit ide of register address 0x05 is set to 1, the STA339BW immediately mutes the i 2 s pcm data out (provided to the processing block) and it freezes any active processing task. to avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any audio streams flowing into STA339BW data path before the desynchronization event table 20. supported serial audio input formats for lsb-first (saifb = 1) bicki sai [3:0] saifb interface format 32 * fs 1100 1 i 2 s 15-bit data 1110 1 left/right-justified 16-bit data 48 * fs 0100 1 i 2 s 23-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data 64 * fs 0000 1 i 2 s 24-bit data 0100 1 i 2 s 20-bit data 1000 1 i 2 s 18-bit data 1100 1 lsb first i 2 s 16-bit data 0001 1 left-justified 24-bit data 0101 1 left-justified 20-bit data 1001 1 left-justified 18-bit data 1101 1 left-justified 16-bit data 0010 1 right-justified 24-bit data 0110 1 right-justified 20-bit data 1010 1 right-justified 18-bit data 1110 1 right-justified 16-bit data
register description STA339BW 32/77 doc id 15251 rev 5 happens. at the same time any processing related to the i 2 c configuration should be issued only after the serial audio interface and the internal pll are synchronous again. note: any mute or volume change causes some delay in the completion of the i 2 c operation due to the soft volume feature. the soft volume phase change must be finished before any clock desynchronization. 6.2.4 delay serial clock enable 6.2.5 channel input mapping each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexib ility in processi ng. the default settings of these registers map each i 2 s input channel to its corresponding processing channel. table 21. delay serial clock enable bit r/w rst name description 5 r/w 0 dscke 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some i 2 s master devices table 22. channel input mapping bit r/w rst name description 6r/w0 c1im 0: processing channel 1 receives left i 2 s input 1: processing channel 1 receives right i 2 s input 7r/w1 c2im 0: processing channel 2 receives left i 2 s input 1: processing channel 2 receives right i 2 s input
STA339BW register description doc id 15251 rev 5 33/77 6.3 configuration register c (addr 0x02) 6.3.1 ffx power output mode the ffx power output mode selects how the ffx output timing is configured. different power devices use different output modes. 6.3.2 ffx compensating pul se size register d7 d6 d5 d4 d3 d2 d1 d0 ocrb reserved csz3 csz2 csz1 csz0 om1 om0 10011111 table 23. ffx power output mode bit r/w rst name description 0r/w1 om0 selects configuration of ffx output. 1r/w1 om1 table 24. output modes om[1,0] output stage mode 00 drop compensation 01 discrete output stage - tapered compensation 10 full power mode 11 variable drop compensation (cszx bits) table 25. ffx compensating pulse size bits bit r/w rst name description 2r/w1 csz0 when om[1,0] = 11, this register determines the size of the ffx compensating pulse from 0 clock ticks to 15 clock periods. 3r/w1 csz1 4r/w1 csz2 5r/w0 csz3 table 26. compensating pulse size csz[3:0] compensating pulse size 0000 0 ns (0 tick) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size ?? 1111 300 ns (15 tick) clock period compensating pulse size
register description STA339BW 34/77 doc id 15251 rev 5 6.3.3 overcurrent warni ng detect adjustment bypass the ocwarn input is used to indicate an overcurrent warning condition. when ocwarn is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 db) in an attempt to eliminate the overcurrent warning condition. once the overcurrent warning volume adjustment is appli ed, it remains in this state until reset is applied. the level of adjustment can be changed via the twocl (thermal warning / overcurrent limit) setting which is address 0x37 of the user defined coefficient ram. 6.4 configuration register d (addr 0x03) 6.4.1 high-pass filter bypass the STA339BW features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc si gnals from passing through a ffx amplifier. dc signals can cause speaker damage. when hpb = 0, this filter is enabled. 6.4.2 de-emphasis 6.4.3 dsp bypass setting the dspb bit bypasses th e eq function of the STA339BW. table 27. overcurrent warning bypass bit r/w rst name description 7 r/w 1 ocrb 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled d7 d6 d5 d4 d3 d2 d1 d0 sme zde drc bql psl dspb demp hpb 01000000 table 28. high-pass filter bypass bit r/w rst name description 0r/w0 hpb setting of one bypasses internal ac coupling digital high-pass filter table 29. de-emphasis bit r/w rst name description 1r/w0 demp 0: no de-emphasis 1: enable de-emphasis on all channels table 30. dsp bypass bit r/w rst name description 2 r/w 0 dspb 0: normal operation 1: bypass of biquad and bass/treble functions
STA339BW register description doc id 15251 rev 5 35/77 6.4.4 post-scale link post-scale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. 6.4.5 biquad coefficient link for ease of use, all channels can use the biquad coefficients loaded into the channel-1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. 6.4.6 dynamic range compre ssion/anti-clipping bit both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. in dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 6.4.7 zero-detect mute enable setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. if any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. table 31. post-scale link bit r/w rst name description 3r/w0 psl 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value table 32. biquad coefficient link bit r/w rst name description 4r/w0 bql 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values table 33. dynamic range compression/anti-clipping bit bit r/w rst name description 5 r/w 0 drc 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode table 34. zero-detect mute enable bit r/w rst name description 6 r/w 1 zde setting of 1 enables the automatic zero-detect mute
register description STA339BW 36/77 doc id 15251 rev 5 6.4.8 submix mode enable 6.5 configuration register e (addr 0x04) 6.5.1 max power correction variable 6.5.2 max power correction setting the mpc bit turns on special processing that corrects the STA339BW power device at high power. this mode should lower the thd+n of a full ffx system at maximum power output and slightly below. if enabled, mpc is operational in all output modes except tapered (om[1,0] = 01) and binary. when ocfg = 00, mpc will not effect channels 3 and 4, the line- out channels. 6.5.3 noise-shaper bandwidth selection table 35. submix mode enable bit r/w rst name description 7r/w0 sme 0: sub mix into left/right disabled 1: sub mix into left/right enabled d7 d6 d5 d4 d3 d2 d1 d0 sve zce dccv pwms ame nsbw mpc mpcv 11000010 table 36. max power correction variable bit r/w rst name description 0r/w0 mpcv 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient table 37. max power correction bit r/w rst name description 1r/w1 mpc setting of 1 enables power bridge correction for thd reduction near maximum power output. table 38. noise-shaper bandwidth selection bit r/w rst name description 2 r/w 0 nsbw 1: third order ns 0: fourth order ns
STA339BW register description doc id 15251 rev 5 37/77 6.5.4 am mode enable STA339BW features affx processing mode that minimizes the amount of noise generated in frequency range of am radio. this mode is intended for use when ffx is operating in a device with an am tuner active. the snr of the ffx processing is reduced to approximately 83 db in this mode, which is still greater than the snr of am radio. 6.5.5 pwm speed mode 6.5.6 distortion compe nsation variable enable 6.5.7 zero-crossing volume enable the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings no clicks are audible. 6.5.8 soft volume update enable table 39. am mode enable bit r/w rst name description 3r/w0 ame 0: normal ffx operation. 1: am reduction mode ffx operation table 40. pwm speed mode bit r/w rst name description 4r/w0 pwms 0: normal speed (384 khz) all channels 1: odd speed (341.3 khz) all channels table 41. distortion compensation variable enable bit r/w rst name description 5 r/w 0 dccv 0: use preset dc coefficient 1: use dcc coefficient table 42. zero-crossing volume enable bit r/w rst name description 6r/w1 zce 1: volume adjustments only occur at digital zero- crossings 0: volume adjustments occur immediately table 43. soft volume update enable bit r/w rst name description 7 r/w 1 sve 1: volume adjustments ramp according to svr settings 0: volume adjustments occur immediately
register description STA339BW 38/77 doc id 15251 rev 5 6.6 configuration register f (addr 0x05) 6.6.1 output configuration note: to the left of the arrow is the processing channel. when using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. d7 d6 d5 d4 d3 d2 d1 d0 eapd pwdn ecle ldte bcle ide ocfg1 ocfg0 01011100 table 44. output configuration bit r/w rst name description 0 r/w 0 ocfg0 selects the output configuration 1 r/w 0 ocfg1 table 45. output configuration engine selection ocfg[1:0] output configuration config pin 00 2 channel (full-bridge) power, 2 channel data-out: 1a/1b 1a/1b 2a/2b 2a/2b lineout1 3a/3b lineout2 4a/4b line out configuration determined by loc register 0 01 2(half-bridge).1(full-bridge) on-board power: 1a 1a binary 0 2a 1b binary 90 3a/3b 2a/2b binary 45 1a/b 3a/b binary 0 2a/b 4a/b binary 90 0 10 2 channel (full-bridge) power, 1 channel ffx: 1a/1b 1a/1b 2a/2b 2a/2b 3a/3b 3a/3b eapdext and twarnext active 0 11 1 channel mono-parallel: 3a 1a/1b w/ c3bo 45 3b 2a/2b w/ c3bo 45 1a/1b 3a/3b 2a/2b 4a/4b 1
STA339BW register description doc id 15251 rev 5 39/77 figure 11. ocfg = 00 (default value) figure 12. ocfg = 01 figure 13. ocfg = 10 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 lpf lineout 1 out3b lpf lineout 2 out4b out4a out3a half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 channel 1 channel 2 half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 2 channel 1 power device out3b out3a eapd channel 3
register description STA339BW 40/77 doc id 15251 rev 5 figure 14. ocfg = 11 the STA339BW can be configured to support different output configurations. for each pwm output channel a pwm slot is defined. a pwm sl ot is always 1 / (8 * fs) seconds length. the pwm slot define the maximum extension for pwm rise and fall edge, that is, rising edge as far as the falling edge cannot range outside pwm slot boundaries. figure 15. output mapping scheme for each configuration the pwm signals from the digital driver are mapped in different ways to the power stage: half bridge half bridge half bridge half bridge out1a out1b out2a out2b channel 3 out3b out4b out4a out3a channel 1 channel 2 ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b ffx ? modulator remap ffx1a ffx1 b ffx2 a ffx 2b out1a out1b out2a out2b power bridge out1a out1b out2a out2b ffx3 a ffx3b ffx4 a ffx 4b out3a out3b out4a out4b
STA339BW register description doc id 15251 rev 5 41/77 2.0 channels, two full bridges (ocfg = 00) z ffx1a -> out1a z ffx1b -> out1b z ffx2a -> out2a z ffx2b -> out2b z ffx3a -> out3a z ffx3b -> out3b z ffx4a -> out4a z ffx4b -> out4b z ffx1a/1b configured as ternary z ffx2a/2b configured as ternary z ffx3a/3b configured as lineout ternary z ffx4a/4b configured as lineout ternary on channel 3 line out (loc bits = 00) the same data as channel 1 processing is sent. on channel 4 line out (loc bits = 00) the same data as channel 2 processing is sent. in this configuration, volume control or eq have no effect on channels 3 and 4. in this configuration the pwm slot phase is the following as shown in figure 16 . figure 16. 2.0 channels (ocfg = 00) pwm slots out1a out1b out2a out2b out3a out3b out4a out4b
register description STA339BW 42/77 doc id 15251 rev 5 2.1 channels, two half bridges + one full bridge (ocfg = 01) z ffx1a -> out1a z ffx2a -> out1b z ffx3a -> out2a z ffx3b -> out2b z ffx1a -> out3a z ffx1b -> out3b z ffx2a -> out4a z ffx2b -> out4b z ffx1a/1b configured as binary z ffx2a/2b configured as binary z ffx3a/3b configured as binary z ffx4a/4b is not used in this configuration, channel 3 has full control (volume, eq, etc?). on out3/out4 channels the channel 1 and channel 2 pwm are replicated. in this configuration the pwm slot phase is the following as shown in figure 17 . figure 17. 2.1 channels (ocfg = 01) pwm slots out1a out2a out2b out3a out3b out1b out4a out4b out1a out2a out2b out3a out3b out1b out4a out4b
STA339BW register description doc id 15251 rev 5 43/77 2.1 channels, two fullbridge + one external full bridge (ocfg = 10) z ffx1a -> out1a z ffx1b -> out1b z ffx2a -> out2a z ffx2b -> out2b z ffx3a -> out3a z ffx3b -> out3b z eapd -> out4a z twarn -> out4b z ffx1a/1b configured as ternary z ffx2a/2b configured as ternary z ffx3a/3b configured as ternary z ffx4a/4b is not used in this configuration, channel 3 has full control (volume, eq, etc?). on out4 channel the external bridge control signals are muxed. in this configuration the pwm slot phase is the following as shown in figure 18 . figure 18. 2.1 channels (ocfg = 10) pwm slots out1a out1b out2a out2b out3a out3b out1a out1b out2a out2b out3a out3b
register description STA339BW 44/77 doc id 15251 rev 5 6.6.2 invalid input detect mute enable setting the ide bit enables this function, which looks at the input i 2 s data and automatically mutes if the signals are perceived as invalid. 6.6.3 binary output mode clock loss detection detects loss of input mclk in bina ry mode and will outpu t 50% duty cycle. 6.6.4 lrck double trigger protection actively prevents double trigger of lrclk. 6.6.5 auto eapd on clock loss when active, issues a power device power down signal (eapd) on clock loss detection. 6.6.6 ic power down the pwdn register is used to place the ic in a low-power state. when pwdn is written as 0, the output begins a soft-mute. after the mute condition is reached, eapd is asserted to power down the power-stage, then the master clock to all internal hardware expect the i 2 c block is gated. this places the ic in a very low power consumption state. table 46. invalid input detect mute enable bit r/w rst name description 2r/w1 ide setting of 1 enables the automatic invalid input detect mute table 47. binary output mode clock loss detection bit r/w rst name description 3 r/w 1 bcle binary output mode clock loss detection enable table 48. lrck double trigger protection bit r/w rst name description 4 r/w 1 ldte lrclk double trigger protection enable table 49. auto eapd on clock loss bit r/w rst name description 5 r/w 0 ecle auto eapd on clock loss table 50. ic power down bit r/w rst name description 7r/w1 pwdn 0: ic power down low-power condition 1: ic normal operation
STA339BW register description doc id 15251 rev 5 45/77 6.6.7 external am plifier power down the eapd register directly disables/enables the internal power circuitry. when eapd = 0, the internal power section is placed on a low-power state (disabled). this register also controls the ffx4b/eapd output pin when ocfg = 10. 6.7 volume control regi sters (addr 0x06 - 0x0a) 6.7.1 mute/line output configuration register line output is only active when ocfg = 00. in this case loc determines the line output configuration. the source of the line output is always the channel 1 and 2 inputs. 6.7.2 master volume register 6.7.3 channel 1 volume 6.7.4 channel 2 volume table 51. external amplifier power down bit r/w rst name description 7r/w0 eapd 0: external power stage power down active 1: normal operation d7 d6 d5 d4 d3 d2 d1 d0 loc1 loc0 reserved c3m c2m c1m mmute 00000000 table 52. line output configuration loc[1:0] line output configuration 00 line output fixed - no volume, no eq 01 line output variable - ch3 volume effects line output, no eq 10 line output variable with eq - ch3 volume effects line output d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000
register description STA339BW 46/77 doc id 15251 rev 5 6.7.5 channel 3 / line output volume the volume structure of the STA339BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. the individual channel volumes are adjustable in 0.5 db steps from +48 db to - 80 db. as an example if c3v = 0x00 or +48 db and mv = 0x18 or -12 db, then the total gain for channel 3 = +36 db. the master mute, when set to 1, mutes all channels at once, whereas the individual channel mutes (cxm) mutes only that channel. both the master mute and the channel mutes provide a ?soft mute? with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 khz). a ?hard (instantaneous) mute? can be obtained by programming a value of 0xff (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register any channel whose total volume is less than -80 db is muted. all changes in volume take place at zero-crossings when zce = 1 ( configuration register e (addr 0x04) on page 36 ) on a per channel basis as this creates the smoothest possible volume transitions. when zce = 0, volume updates occur immediately. d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 table 53. master volume offset as a function of mv[7:0] mv[7:0] volume offset from channel value 00000000 (0x00) 0 db 00000001 (0x01) -0.5 db 00000010 (0x02) -1 db ?? 01001100 (0x4c) -38 db ?? 11111110 (0xfe) -127.5 db 11111111 (0xff) hard master mute table 54. channel volume as a function of cxv[7:0] cxv[7:0] volume 00000000 (0x00) +48 db 00000001 (0x01) +47.5 db 00000010 (0x02) +47 db ?? 01011111 (0x5f) +0.5 db 01100000 (0x60) 0 db
STA339BW register description doc id 15251 rev 5 47/77 6.8 audio preset register s (addr 0x0b and 0x0c) 6.8.1 audio preset r egister 1 (addr 0x0b) using amgc[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. amgc[3:2] is defined in register eq coefficients and drc configuration register (addr 0x31) on page 65 . the amgc[1:0] bits behave in two different ways depending on the value of amgc[3:2]. when this value is 00 then bits amgc[1:0] are defined below in ta b l e 5 5 . 6.8.2 audio preset r egister 2 (addr 0x0c) 01100001 (0x61) -0.5 db ?? 11010111 (0xd7) -59.5 db 11011000 (0xd8) -60 db 11011001 (0xd9) -61 db 11011010 (0xda) -62 db ?? 11101100 (0xec) -80 db 11101101 (0xed) hard channel mute ?? 11111111 (0xff) hard channel mute table 54. channel volume as a function of cxv[7:0] (continued) cxv[7:0] volume d7 d6 d5 d4 d3 d2 d1 d0 reserved amgc[1] amgc[0] reserved 00000000 table 55. audio preset gain compression/limiters selection for amgc[3:2] = 00 amgc[1:0] mode 00 user programmable gc 01 ac no clipping 2.1 10 ac limited clipping (10%) 2.1 11 drc night-time listening mode 2.1 d7 d6 d5 d4 d3 d2 d1 d0 xo3 xo2 xo1 xo0 amam2 amam1 amam0 amame 00000000
register description STA339BW 48/77 doc id 15251 rev 5 6.8.3 am interference frequency switching 6.8.4 bass management crossover table 56. am interference frequency switching bits bit r/w rst name description 0 r/w 0 amame audio preset am enable 0: switching frequency determined by pwms setting 1: switching frequency determined by amam settings table 57. audio preset am switching frequency selection amam[2:0] 48 khz/96 khz input fs 44.1 khz/88.2 khz input fs 000 0.535 mhz - 0.720 mhz 0.535 mhz - 0.670 mhz 001 0.721 mhz - 0.900 mhz 0.671 mhz - 0.800 mhz 010 0.901 mhz - 1.100 mhz 0.801 mhz - 1.000 mhz 011 1.101 mhz - 1.300 mhz 1.001 mhz - 1.180 mhz 100 1.301 mhz - 1.480 mhz 1.181 mhz - 1.340 mhz 101 1.481 mhz - 1.600 mhz 1.341 mhz - 1.500 mhz 110 1.601 mhz - 1.700 mhz 1.501 mhz - 1.700 mhz table 58. bass management crossover bit r/w rst name description 4r/w0 xo0 selects the bass-management crossover frequency. a 1st-order hign-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed. 5r/w0 xo1 6r/w0 xo2 7r/w0 xo3 table 59. bass management crossover frequency xo[3:0] crossover frequency 0000 user-defined 0001 80 hz 0010 100 hz 0011 120 hz 0100 140 hz 0101 160 hz 0110 180 hz 0111 200 hz 1000 220 hz 1001 240 hz
STA339BW register description doc id 15251 rev 5 49/77 6.9 channel configuration registers (addr 0x0e - 0x10) 6.9.1 tone control bypass tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2. 6.9.2 eq bypass eq control can be bypassed on a per channel basis for channels 1 and 2. if eq control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. 1010 260 hz 1011 280 hz 1100 300 hz 1101 320 hz 1110 340 hz 1111 360 hz table 59. bass management crossover frequency (continued) xo[3:0] crossover frequency d7 d6 d5 d4 d3 d2 d1 d0 c1om1 c1om0 c1ls1 c1ls0 c1bo c1vpb c1eqbp c1tcb 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2om1 c2om0 c2ls1 c2ls0 c2bo c2vpb c2eqbp c2tcb 01000000 d7 d6 d5 d4 d3 d2 d1 d0 c3om1 c3om0 c3ls1 c3ls0 c3bo c3vpb reserved 10000000 table 60. tone control bypass cxtcb mode 0 perform tone control on channel x - normal operation 1 bypass tone control on channel x table 61. eq bypass cxeqbp mode 0 perform eq on channel x - normal operation 1 bypass eq on channel x
register description STA339BW 50/77 doc id 15251 rev 5 6.9.3 volume bypass each channel contains an individual channel volume bypass. if a particular channel has volume bypassed via the cxvbp = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volu me setting will not affect that channel. 6.9.4 binary output enable registers each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel is considered the positive output and output b is negative inverse. 6.9.5 limiter select limiter selection can be made on a per-channel basis according to the channel limiter select bits. . 6.9.6 output mapping output mapping can be performed on a per channel basis according to the cxom channel output mapping bits. each input into the output configuration engine can receive data from any of the three processing channel outputs. . table 62. binary output enable registers cxbo mode 0 ffx 3-state output - normal operation 1 binary output table 63. channel limiter mapping as a function of cxls bits cxls[1:0] channel limiter mapping 00 channel has limiting disabled 01 channel is mapped to limiter #1 10 channel is mapped to limiter #2 table 64. channel output mapping as a function of cxom bits cxom[1:0] channel x output source from 00 channel1 01 channel 2 10 channel 3
STA339BW register description doc id 15251 rev 5 51/77 6.10 tone control register (addr 0x11) 6.10.1 tone control 6.11 dynamic control registers (addr 0x12 - 0x15) 6.11.1 limiter 1 attack/release rate 6.11.2 limiter 1 attack/release threshold 6.11.3 limiter 2 attack/release rate d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 table 65. tone control boost/cut as a function of btc and ttc bits btc[3:0]/ttc[3:0] boost/cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12 db d7 d6 d5 d4 d3 d2 d1 d0 l1a3 l1a2 l1a1 l1a0 l1r3 l1r2 l1r1 l1r0 01101010 d7 d6 d5 d4 d3 d2 d1 d0 l1at3 l1at2 l1at1 l1at0 l1rt3 l1rt2 l1rt1 l1rt0 01101001 d7 d6 d5 d4 d3 d2 d1 d0 l2a3 l2a2 l2a1 l2a0 l2r3 l2r2 l2r1 l2r0 01101010
register description STA339BW 52/77 doc id 15251 rev 5 6.11.4 limiter 2 attack/release threshold the STA339BW includes two independent limiter blocks. the purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively redu ce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for dvds. the two modes are selected via the drc bit in configuration register e (addr 0x04) on page 36 . each channel can be mapped to either limiter or no t mapped, meaning th at channel will clip when 0 dbfs is exceeded. each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison. the limiter attack thresholds are determined by the lxat registers if eathx[7] bits are set to 0 else the thresholds are determined by eathx[6:0] . it is recommended in anti-clipping mode to set this to 0 dbfs, which corresponds to the maximum unclipped output power of a ffx amplifier. since gain can be added digitally within the STA339BW it is possible to exceed 0 dbfs or any other lxat setting, when this occurs, the limiter, when active, automatically starts reducing the gain. the rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. gain reduction occurs on a peak-detect algorithm. setting eathx[7] bits to 1 selects the anti-clipping mode. the limiter release thresholds are determined by the lxrt registers if erthx[7] bits are set to 0 else the thresholds are determined by erthx[6:0]. settings to 1 erthx[7] bits the anti-clipping mode is selected automatically. the release of limiter, when the gain is again increased, is dependent on a rms-detect algorithm. the output of the volume/limiter block is passed through a rms filter. the output of this filter is compared to the release threshold, determined by the release threshold register. when the rms filter output falls below the release threshold, the gain is again increased at a rate dependent upon the release rate register. the gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. the release threshold value can be used to set what is effectively a minimum dynamic range, this is helpfu l as over-limiting can reduce the dynamic range to virtually zero a nd cause program material to sound ?lifeless?. in ac mode, the attack and re lease thresholds are set relati ve to full-scale. in drc mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is se t relative to the maximum volume setting plus the attack threshold. d7 d6 d5 d4 d3 d2 d1 d0 l2at3 l2at2 l2at1 l2at0 l2rt3 l2rt2 l2rt1 l2rt0 01101001
STA339BW register description doc id 15251 rev 5 53/77 figure 19. basic limiter and volume flow diagram table 66. limiter attack rate as a function of lxa bits table 67. limiter release rate as a function of lxr bits lxa[3:0] attack rate db/ms lxr[3:0] release rate db/ms 0000 3.1584 fast slow 0000 0.5116 fast slow 0001 2.7072 0001 0.1370 0010 2.2560 0010 0.0744 0011 1.8048 0011 0.0499 0100 1.3536 0100 0.0360 0101 0.9024 0101 0.0299 0110 0.4512 0110 0.0264 0111 0.2256 0111 0.0208 1000 0.1504 1000 0.0198 1001 0.1123 1001 0.0172 1010 0.0902 1010 0.0147 1011 0.0752 1011 0.0137 1100 0.0645 1100 0.0134 1101 0.0564 1101 0.0117 1110 0.0501 1110 0.0110 1111 0.0451 1111 0.0104
register description STA339BW 54/77 doc id 15251 rev 5 anti-clipping mode table 68. limiter attack threshold as a function of lxat bits (ac mode) table 69. limiter release threshold as a function of lxrt bits (ac mode) lxat[3:0] ac (db relative to fs) l xrt[3:0] ac (db relative to fs) 0000 -12 0000 - 0001 -10 0001 -29 db 0010 -8 0010 -20 db 0011 -6 0011 -16 db 0100 -4 0100 -14 db 0101 -2 0101 -12 db 0110 0 0110 -10 db 0111 +2 0111 -8 db 1000 +3 1000 -7 db 1001 +4 1001 -6 db 1010 +5 1010 -5 db 1011 +6 1011 -4 db 1100 +7 1100 -3 db 1101 +8 1101 -2 db 1110 +9 1110 -1 db 1111 +10 1111 -0 db
STA339BW register description doc id 15251 rev 5 55/77 dynamic range compression mode 6.11.5 limiter 1 extended at tack threshold (addr 0x32) the extended attack threshold value is determined as follows: attack threshold = -12 + eath1 / 4 6.11.6 limiter 1 extended re lease threshold (addr 0x33) the extended release threshold value is determined as follows: release threshold = -12 + erth1 / 4 table 70. limiter attack threshold as a function of lxat bits (drc mode) table 71. limiter release threshold as a as a function of lxrt bits (drc mode) lxat[3:0] drc (db relative to volume) lxrt[3:0] drc (db relative to volume + lxat) 0000 -31 0000 - 0001 -29 0001 -38 db 0010 -27 0010 -36 db 0011 -25 0011 -33 db 0100 -23 0100 -31 db 0101 -21 0101 -30 db 0110 -19 0110 -28 db 0111 -17 0111 -26 db 1000 -16 1000 -24 db 1001 -15 1001 -22 db 1010 -14 1010 -20 db 1011 -13 1011 -18 db 1100 -12 1100 -15 db 1101 -10 1101 -12 db 1110 -7 1110 -9 db 1111 -4 1111 -6 db d7 d6 d5 d4 d3 d2 d1 d0 eathen1eath1[6]eath1[5]eath1[4]eath1[3]eath1[2]eath1[1]eath1[0] tbdtbdtbdtbdtbdtbdtbdtbd d7 d6 d5 d4 d3 d2 d1 d0 erthen1 erth1[6] erth1[5] erth1[4] erth1[3] erth1[2] erth1[1] erth1[0] tbdtbdtbdtbdtbdtbdtbdtbd
register description STA339BW 56/77 doc id 15251 rev 5 6.11.7 limiter 2 extended at tack threshold (addr 0x34) the extended attack threshold value is determined as follows: attack threshold = -12 + eath2 / 4 6.11.8 limiter 2 extended re lease threshold (addr 0x35) the extended release threshold value is determined as follows: release threshold = -12 + erth2 / 4 note: attack/release threshold step is 0.125 db in the range -12 db and 0 db. 6.12 user-defined coefficient cont rol registers (addr 0x16 - 0x26) 6.12.1 coefficient address register 6.12.2 coefficient b1 data register bits 23:16 6.12.3 coefficient b1 dat a register bits 15:8 6.12.4 coefficient b1 dat a register bits 7:0 d7 d6 d5 d4 d3 d2 d1 d0 eathen2eath2[6]eath2[5]eath2[4]eath2[3]eath2[2]eath2[1]eath2[0] tbdtbdtbdtbdtbdtbdtbdtbd d7 d6 d5 d4 d3 d2 d1 d0 erthen2 erth2[6] erth2[5] erth2[4] erth2[3] erth2[2] erth2[1] erth2[0] tbdtbdtbdtbdtbdtbdtbdtbd d7 d6 d5 d4 d3 d2 d1 d0 reserved cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0 000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000
STA339BW register description doc id 15251 rev 5 57/77 6.12.5 coefficient b2 data register bits 23:16 6.12.6 coefficient b2 dat a register bits 15:8 6.12.7 coefficient b2 dat a register bits 7:0 6.12.8 coefficient a1 data register bits 23:16 6.12.9 coefficient a1 dat a register bits 15:8 6.12.10 coefficient a1 dat a register bits 7:0 6.12.11 coefficient a2 dat a register bits 23:16 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000
register description STA339BW 58/77 doc id 15251 rev 5 6.12.12 coefficient a2 dat a register bits 15:8 6.12.13 coefficient a2 dat a register bits 7:0 6.12.14 coefficient b0 dat a register bits 23:16 6.12.15 coefficient b0 dat a register bits 15:8 6.12.16 coefficient b0 dat a register bits 7:0 6.12.17 coefficient write /read control register coefficients for user-defined eq, mixing, scaling, and bass management are handled internally in the STA339BW via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this function. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from ram. three different ram banks are embedded in STA339BW. the three banks are managed in paging mode using eqcfg register bits. they can be used to store different eq settings. for speaker frequency compensation, a sampling frequency independent eq must be implemented. computing three different coefficients set for 32 khz, 44.1khz, 48 khz and downloading them into the three ram banks, it is possible to select the suitable ram block depending from the incoming frequency with a simple i 2 c write operation on register 0x31. d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved ra r1 wa w1 0 0000
STA339BW register description doc id 15251 rev 5 59/77 for example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three ram blocks allowing a faster operation, without any additional download from the microcontroller. to write the coefficients in a particular ram bank, this bank must be selected first writing bit 0 and bit 1 in register 0x31. then the write procedure below can be used. note that as soon as a ram bank is selected, the eq settings are automatically switched to the coefficients stored in the active ram block. note: the read and write operation on ram coefficients works only if lrcki (pin 29) is switching. reading a coefficient from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6 bits of address to i 2 c register 0x16. 3. write 1 to r1 bit in i 2 c address 0x26. 4. read top 8 bits of coefficient in i 2 c address 0x17. 5. read middle 8 bits of coefficient in i 2 c address 0x18. 6. read bottom 8 bits of coefficient in i 2 c address 0x19. reading a set of coefficients from ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6 bits of address to i 2 c register 0x16. 3. write 1 to ra bit in i 2 c address 0x26. 4. read top 8 bits of coefficient in i 2 c address 0x17. 5. read middle 8 bits of coefficient in i 2 c address 0x18. 6. read bottom 8 bits of coefficient in i 2 c address 0x19. 7. read top 8 bits of coefficient b2 in i 2 c address 0x1a. 8. read middle 8 bits of coefficient b2 in i 2 c address 0x1b. 9. read bottom 8 bits of coefficient b2 in i 2 c address 0x1c. 10. read top 8 bits of coefficient a1 in i 2 c address 0x1d. 11. read middle 8 bits of coefficient a1 in i 2 c address 0x1e. 12. read bottom 8 bits of coefficient a1 in i 2 c address 0x1f. 13. read top 8 bits of coefficient a2 in i 2 c address 0x20. 14. read middle 8 bits of coefficient a2 in i 2 c address 0x21. 15. read bottom 8 bits of coefficient a2 in i 2 c address 0x22. 16. read top 8 bits of coefficient b0 in i 2 c address 0x23. 17. read middle 8 bits of coefficient b0 in i 2 c address 0x24. 18. read bottom 8 bits of coefficient b0 in i 2 c address 0x25.
register description STA339BW 60/77 doc id 15251 rev 5 writing a single coefficient to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6 bits of address to i 2 c register 0x16. 3. write top 8 bits of coefficient in i 2 c address 0x17. 4. write middle 8 bits of coefficient in i 2 c address 0x18. 5. write bottom 8 bits of coefficient in i 2 c address 0x19. 6. write 1 to w1 bit in i 2 c address 0x26. writing a set of coefficients to ram 1. select the ram block with register 0x31 bit1, bit0. 2. write 6 bits of starting address to i 2 c register 0x16. 3. write top 8 bits of coefficient b1 in i 2 c address 0x17. 4. write middle 8 bits of coefficient b1 in i 2 c address 0x18. 5. write bottom 8 bits of coefficient b1 in i 2 c address 0x19. 6. write top 8 bits of coefficient b2 in i 2 c address 0x1a. 7. write middle 8 bits of coefficient b2 in i 2 c address 0x1b. 8. write bottom 8 bits of coefficient b2 in i 2 c address 0x1c. 9. write top 8 bits of coefficient a1 in i 2 c address 0x1d. 10. write middle 8 bits of coefficient a1 in i 2 c address 0x1e. 11. write bottom 8 bits of coefficient a1 in i 2 c address 0x1f. 12. write top 8 bits of coefficient a2 in i 2 c address 0x20. 13. write middle 8 bits of coefficient a2 in i 2 c address 0x21. 14. write bottom 8 bits of coefficient a2 in i 2 c address 0x22. 15. write top 8 bits of coefficient b0 in i 2 c address 0x23. 16. write middle 8 bits of coefficient b0 in i 2 c address 0x24. 17. write bottom 8 bits of coefficient b0 in i 2 c address 0x25. 18. write 1 to wa bit in i 2 c address 0x26. the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA339BW generates the ram addresses as offsets from this base value to write the complete set of coefficient data.
STA339BW register description doc id 15251 rev 5 61/77 6.12.18 user-defined eq the STA339BW can be programmed for four eq filters (biquads) per each of the two input channels. the biquads use the following equation: y[n] = 2 * (b 0 / 2) * x[n] + 2 * (b 1 / 2) * x[n-1] + b 2 * x[n-2] - 2 * (a 1 / 2) * y[n-1] - a 2 * y[n-2] = b 0 * x[n] + b 1 * x[n-1] + b 2 * x[n-2] - a 1 * y[n-1] - a 2 * y[n-2] where y[n] represents the output and x[n] represents the input. multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7fffff (0.9999998808). coefficients stored in the user defined coe fficient ram are referenced in the following manner: cxhy0 = b 1 / 2 cxhy1 = b 2 cxhy2 = -a 1 / 2 cxhy3 = -a 2 cxhy4 = b 0 / 2 where x represents the channel and the y the biquad number. for example, c2h41 is the b 2 coefficient in the fourth biquad for channel 2. additionally, the STA339BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bass-management crossover when the xo setting is 000 (user-defined). both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. they are loaded into the c12h0-4 and c3hy0-4 areas of ram noted in ta b l e 7 2 . by default, all user-defined filters are pass-through where all coefficients are set to 0, except the b 0 /2 coefficient which is set to 0x400000 (representing 0.5) 6.12.19 prescale the STA339BW provides a multiplication for each input channel for the purpose of scaling the input prior to eq. this pre-eq scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiplication is loade d into ram using the same i 2 c registers as the biquad coefficients and the bass management. all channels can use the channel-1 prescale factor by setting the biquad link bit. by default, all prescale factors are set to 0x7fffff. 6.12.20 postscale the STA339BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. this postscaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. the scale factor for this multiply is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass management. this postscale factor can be used in conjunction with an adc equipped microcontroller to perform power-supply error correction. all channels can use the channel-1 postscale factor by setting the postscale link bit. by default, all postscale factors are set to 0x7fffff. when line output is being used, channel-3 postscale will affect both channels 3 and 4.
register description STA339BW 62/77 doc id 15251 rev 5 6.12.21 overcurrent postscale the STA339BW provides a simple mechanism for reacting to overcurrent detection in the power block. when the ocwarn input is asserted, the overcurrent postscale value is used in place of the normal postscale value to provide output attenuation on all channels. the default setting provides 3 db of output attenuation when ocwarn is asserted. the amount of attenuation to be applied in this situation can be adjusted by modifying the overcurrent postscale value. as with the norma l postscale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7fffff = 0.9999998808. by default, the overcurrent postscale factor is set to 0x5a9df7 . once the overcurrent attenuation is applied, it remains unt il the device is reset. table 72. ram block for biquads, mixing, scaling and bass management index (decimal) index (hex) ram block setting coefficient default 0 0x00 channel 1 - biquad 1 c1h10(b1/2) 0x000000 1 0x01 c1h11(b2) 0x000000 2 0x02 c1h12(a1/2) 0x000000 3 0x03 c1h13(a2) 0x000000 4 0x04 c1h14(b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000 ??? ? ? 19 0x13 channel 1 - biquad 4 c1h44 0x400000 20 0x14 channel 2 - biquad 1 c2h10 0x000000 21 0x15 c2h11 0x000000 ??? ? ? 39 0x27 channel 2 - biquad 4 c2h44 0x400000 40 0x28 channel 1/2 - biquad 5 for xo = 000 high-pass 2 nd order filter for xo 000 c12h0(b1/2) 0x000000 41 0x29 c12h1(b2) 0x000000 42 0x2a c12h2(a1/2) 0x000000 43 0x2b c12h3(a2) 0x000000 44 0x2c c12h4(b0/2) 0x400000 45 0x2d channel 3 - biquad for xo = 000 low-pass 2 nd order filter for xo 000 c3h0(b1/2) 0x000000 46 0x2e c3h1(b2) 0x000000 47 0x2f c3h2(a1/2) 0x000000 48 0x30 c3h3(a2) 0x000000 49 0x31 c3h4(b0/2) 0x400000 50 0x32 channel 1 - prescale c1pres 0x7fffff 51 0x33 channel 2 - prescale c2pres 0x7fffff 52 0x34 channel 1 - postscale c1psts 0x7fffff 53 0x35 channel 2 - postscale c2psts 0x7fffff
STA339BW register description doc id 15251 rev 5 63/77 6.13 variable max power correction registers (addr 0x27 - 0x28) mpcc bits determine the 16 msbs of the mpc comp ensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 6.14 variable distortion compen sation registers (addr 0x29 - 0x2a) dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of the default coefficient when dccv = 1. 54 0x36 channel 3 - postscale c3psts 0x7fffff 55 0x37 twarn/oc - limit twocl 0x5a9df7 56 0x38 channel 1 - mix 1 c1mx1 0x7fffff 57 0x39 channel 1 - mix 2 c1mx2 0x000000 58 0x3a channel 2 - mix 1 c2mx1 0x000000 59 0x3b channel 2 - mix 2 c2mx2 0x7fffff 60 0x3c channel 3 - mix 1 c3mx1 0x400000 61 0x3d channel 3 - mix 2 c3mx2 0x400000 62 0x3e unused - - 63 0x3f unused - - table 72. ram block for biquads, mixing, scaling and bass management (continued) index (decimal) index (hex) ram block setting coefficient default d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00011010 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011
register description STA339BW 64/77 doc id 15251 rev 5 6.15 fault detect recovery consta nt registers (addr 0x2b - 0x2c) fdrc bits specify the 16-bit faul t detect recovery time delay. when fault is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. a constant value of 0x0001 in this register is approximately 0.083 ms. the default value of 0x000c gives approximately 0.1 ms. 6.16 device status register (addr 0x2d) this read-only register provides fault- and thermal-warning status information from the power control block. logic value 1 for faults or warning means normal state. logic 0 means a fault or warning has been detected on the power bridge. the pllul = 1 means that the pll is not locked. d7 d6 d5 d4 d3 d2 d1 d0 fdrc15 fdrc14 fdrc13 fdrc12 fdrc11 fdrc10 fdrc9 fdrc8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 fdrc7 fdrc6 fdrc5 fdrc4 fdrc3 fdrc2 fdrc1 fdrc0 00001100 d7 d6 d5 d4 d3 d2 d1 d0 pllul fault uvfault ovfault ocfault ocwarn tfault twarn table 73. status register bits bit r/w rst name description 7 r - pllul 0: pll locked 1: pll not locked 6r - fault 0: fault detected on power bridge 1: normal operation 5r - uvfault 0: vccxx internally detected 1: undervoltage threshold 4r - ovfault 0: vccxx internally detected 1: overvoltage threshold 3 r - ocfault 0: overcurrent fault detected 2 r - ocwarn 0: overcurrent warning 1 r - tfault 0: thermal fault, junction temperature over limit 0r - twarn 0: thermal warning, junction temperature is close to fault condition
STA339BW register description doc id 15251 rev 5 65/77 6.17 eq coefficients and drc conf iguration register (addr 0x31) bits amgc[3:2] change the behavior of the bits amgc[1:0] as given in ta b l e 7 5 below. when amgc[3:2] = 01 then the bits 1:0 are defined as given here in ta bl e 7 6 . ac0, ac1, ac2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artefacts introduced by ty pical anti-clipping/drc algorithms. more detailed information is available in the applications notes ?configurable output power rate using sta335bw? and ?sta335bws vs sta335bw?. bit xob can be used to bypass the crossover filters. logic 1 means that the function is not active. in this case, high pass crossover filter works as a passtrough on the data path (b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0). 6.18 extended configurat ion register (addr 0x36) extended configuration register provides access to b 2 drc and biquads 5, 6 and 7. d7 d6 d5 d4 d3 d2 d1 d0 xob reserved amgc[3] amgc[2] reserved sel[1] sel[0] 00000000 table 74. eq ram select sel[1:0] eq ram bank selected 00/11 bank 0 activated 01 bank 1 activated 10 bank 2 activated table 75. anti-clipping and drc preset amgc[3:2] anti-clipping and drc preset selected 00 drc/anti-clipping behavior described in table 55 on page 47 (default). 01 drc/anti-clipping behavior is described in ta b l e 7 6 below 10/11 reserved, do not use table 76. anti-clipping selection for amgc[3:2] = 01 amgc[1:0] mode 00 ac0, stereo anticlipping 0 db limiter 01 ac1, stereo anticlipping +1.25 db limiter 10 ac2, stereo anticlipping +2 db limiter 11 reserved do not use d7 d6 d5 d4 d3 d2 d1 d0 mdrc[1] mdrc[0] ps48db xar1 xar2 bq5 bq6 bq7 00000000
register description STA339BW 66/77 doc id 15251 rev 5 6.18.1 dual-band drc the STA339BW provides a dual-band drc (b 2 drc) on the left- and right-channel data path, as depicted in figure 20 . dual-band drc is activated by setting mdrc[1:0] = 1x. figure 20. b 2 drc scheme the low-frequency information (lfe) is extracted from the left and right channels by removing the high frequencies with a programmable biquad filter, so that, using the original signal, the difference signal can be computed. limiter 1 (drc1) is then used to control the left and right high-frequency component amplitudes while limiter 2 (drc2) is used to control the low-frequency components (see chapter 6.11 ). the cutoff frequency of the high-pass filters can be user defined, xo[3:0] = 0, or selected from the pre-defined values. drc1 and drc2 are then used to independently limit the left- and right-channel high frequencies and the lfe-channel amplitude (see chapter 6.11 ) as well as their volume control. note that, in this configuration, the dedicated channel-3 volume control can actually be used as a bass boost enhancer as well (0.5 db/step resolution). the processed lfe channel is then recombined with the l and r channels in order to reconstruct the 2.0 output signal. sub band decomposition the sub band decomposition for b 2 drc can be configured specifying the cutoff frequency. the cut off frequency can be programmed in two ways, using xo bits in register 0x0c, or using ?user programmable? mode (coefficients stored in ram adresses 0x28 to 0x31). for the user programmable mode, use the formulae below to compute the high pass filters: where alpha = (1-sin( 0 ))/cos( 0 ), and 0 is the cutoff frequency. b0 = (1 + alpha) / 2 a0 = 1 b1 = -(1 + alpha) / 2 a1 = -alpha b2 = 0 a2 = 0 r l pass xo filter pass xo filter r l b 2 drc hi-pass filter b 2 drc hi-pass filter - - ch1 volume vol and limiter drc1 ch2 volume drc1 ch3 volume vol and limiter drc2 ch3 volume vol and limiter drc2 + + r l pass xo filter pass xo filter r l b 2 drc hi-pass filter b 2 drc hi-pass filter - - ch1 volume vol and limiter drc1 ch2 volume drc1 ch3 volume vol and limiter drc2 ch3 volume vol and limiter drc2 + +
STA339BW register description doc id 15251 rev 5 67/77 a first-order filter is suggested to guarantee that for every 0 the corresponding low-pass filter obtained as difference (as shown in figure 20 ) will have a symmetric (relative to hp filter) frequency response, and the corresponding recombination after the drc has low ripple. second-order filters can be used as well, but in this case the filter shape must be carefully choosen to provide good low pass response and minimum ripple recombination. for second-order is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done. drc settings the drc blocks used by b 2 drc are the same as those described in chapter 6.11 . b 2 drc configure automatically the drc blocks in anticlipping mode. attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14. band downmixing the low-frequency band is down-mixed to the left and right channels at the b 2 drc output. channel volume can be used to weight the bands recombination to fine tune the overall frequency response. 6.18.2 eq drc mode setting mdrc = 01, it is possible to add a programmable biquad (the xo biquad at ram addresses 0x28 to 0x2c is used for this pur pose) to the limiter/compressor measure path (side chain). using eqdrc the peak detector input can be shaped in frequency using the programmable biquad. for example if a +2 db ba ss boost is applied (using a low shelf filter for example), the effect is that the eqdrc out will limit bass frequencies to -2 db below the selected attack treshold. generally speaking, if the biquad boosts frequency f with an amount of x db, the level of a compressed sinusoid at the output will be th - x, where th is the selected attack threshold. note: eqdrc works only if the biquad frequency response magnitude is >= 0 db for every frequency. figure 21. eqdrc scheme channel in peak detector attenuation calculator atten channel in biquad peak detector attenuation calculator atten eqdrc standard drc channel in peak detector attenuation calculator atten channel in biquad peak detector attenuation calculator atten eqdrc standard drc
register description STA339BW 68/77 doc id 15251 rev 5 6.18.3 extended post scale range post scale is an attenuation by default. when ps48db is set to 1, a 48-db offset is applied to the configured word, so postscale can act as a gain too. 6.18.4 extended attack rate the attack rate shown in ta bl e 6 6 can be extended to provide up to 8 db/ms attack rate on both limiters. table 77. post scale setup ps48db mode 0 postscale value is applied as defined in coefficient ram 1 postscale value is applied with +48-db offset with respect to the coefficient ram value table 78. extended attack rate setup for limiter 1 xar1 mode 0 limiter1 attack rate is configured using ta b l e 6 6 1 limiter1 attack rate is 8 db/ms table 79. extended attack rate setup for limiter 2 xar2 mode 0 limiter2 attack rate is configured using ta b l e 6 6 1 limiter2 attack rate is 8 db/ms
STA339BW register description doc id 15251 rev 5 69/77 6.18.5 extended biquad selector de-ephasis filter as well as bass and treble c ontrols can be configured as user defined filters when equalization coefficients link is activated (bql = 1) and the corresponding bqx bit is set to 1. when filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (bq5), 0x25-0x29 (bq6), 0x2a- 0x2e (bq7) as in ta bl e 7 2 . note: bqx bits are ignored if bql = 0 or if demp = 1 (relevant for bq5) or cxtcb = 1 (relevant for bq6 and bq7). 6.19 eq soft volume configurat ion registers (addr 0x37 - 0x38) soft volume update has a fixed rate by default. using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates. it is also possible to independently define the fade-in (volume is increased) and fade-out (volume is decreased) rates according to the desired behavior. table 80. de-emphasis filter setup bq5 mode 0 preset de-emphasis filter selected 1 user defined biquad 5 coefficients are selected table 81. bass filter setup bq6 mode 0 preset bass filter selected as per ta bl e 6 5 1 user defined biquad 6 coefficients are selected table 82. treble filter setup bq7 mode 0 preset treble filter selected as per ta b l e 6 5 1 user defined biquad 7 coefficients are selected d7 d6 d5 d4 d3 d2 d1 d0 reserved svupe svup[4] svup[3] svup[2] svup[1] svup[0] 00000000 d7 d6 d5 d4 d3 d2 d1 d0 reserved svdwe svdw4] svdw[3] svdw[2] svdw[1] svdw[0] 00000000
register description STA339BW 70/77 doc id 15251 rev 5 when svupe = 1 the fade-in rate is defined by the svup[4:0] bits according to the formula: fade-in rate = 48 / (svup[4:0] + 1) db/ms. when svdwe = 1 the fade-out rate is defined by the svdw[4:0] bits according to the formula: fade-in rate = 48 / (svdw[4:0] + 1) db/ms. 6.20 drc rms filter coefficients (addr 0x39 - 0x3e) signal level detection in drc algorithm is computed usign the following formula: y(t) = c0 * abs(x( t)) + c1 * y(t-1) where x(t) represents the audio signal applied to the limiter, and y(t) the measured level. table 83. soft volume (increasing) setup svupe mode 0 when volume is increased, use the default rate 1 when volume is increased, use the rates defined by svup[4:0] . table 84. soft volume (decreasing) setup svdwe mode 0 when volume is decreased, use the default rate 1 when volume is decreased, use the rates defined by svdw[4:0] . d7 d6 d5 d4 d3 d2 d1 d0 r_c0[23] r_c0[22] r_c0[21] r_c0[20] r_c0[19] r_c0[18] r_c0[17] r_c0[16] 00000001 d7 d6 d5 d4 d3 d2 d1 d0 r_c0[15] r_c0[14] r_c0[13] r_c0[12] r_c0[11] r_c0[10] r_c0[9] r_c0[8] 11101110 d7 d6 d5 d4 d3 d2 d1 d0 r_c0[7] r_c0[6] r_c0[5] r_c0[4] r_c0[3] r_c0[2] r_c0[1] r_c0[0] 11111111 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[23] r_c1[22] r_c1[21] r_c1[20] r_c1[19] r_c1[18] r_c1[17] r_c1[16] 01111110 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[15] r_c1[14] r_c1[13] r_c1[12] r_c1[11] r_c1[10] r_c1[9] r_c1[8] 11000000 d7 d6 d5 d4 d3 d2 d1 d0 r_c1[7] r_c1[6] r_c1[5] r_c1[4] r_c1[3] r_c1[2] r_c1[1] r_c1[0] 00100110
STA339BW application doc id 15251 rev 5 71/77 7 application 7.1 application scheme for power supplies here in figure 22 below is the typical application di agram for STA339BW showing the power supply decoupling. particular care has to be taken with the layout of the pcb. in particular the 3.3 ? resistors on the digital supplies (vdd_dig) have to be placed as close as possible to the device. this helps to prevent unwanted osc illation in the digital part of the device due to the inductive tracks of the pcb. the same rule also applies to all the decoulpling capacitors in order to limit spikes on all the supplies. figure 22. application diagram 7.2 pll filter it is recommended to use the above scheme and values for the pll filter to achieve the best performance from the device in general applications. note that the ground of this filter circuit has to be connected to the ground of the pll without any resistive path. concerning the component values, remember that the greater is the filter bandwidth, the less is the lock time but the higher is the pll output jitter.
application STA339BW 72/77 doc id 15251 rev 5 7.3 typical output configuration here after the typical output configuration used for btl stereo mode. please refer to the application note for all the other possible output configuration recommended schematics. figure 23. output configuration for stereo btl mode 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 left 100nf 6.2 out1a out1b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2 22uh 22uh 100nf 100nf 470nf 330pf 100nf 22 right 100nf 6.2 out2a out2b 6.2
STA339BW package thermal characteristics doc id 15251 rev 5 73/77 8 package thermal characteristics using a double-layer pcb the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm 2 and with 16 via holes (see figure 24 ) is 24 c/w in natural air convection. the dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. thus, the maximum estimated dissipa ted power for the STA339BW is: figure 24. double-layer pcb with 2 copper ground areas and 16 via holes figure 25 shows the power derating curve for the powersso-36 slug-down package on pcbs with copper areas of 2 x 2 cm 2 and 3 x 3 cm 2 . figure 25. powersso-36 power derating curve 2 x 20 w @ 8 ? , 18 v pd max ~ 4 w 2 x 10 w + 1 x 20 w @ 4 ? , 8 ? , 18 v pd max < 5 w 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes STA339BW psso36 copper area 3x3 cm and via holes 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 pd (w) tamb ( c) copper area 2x2 cm and via holes STA339BW psso36 copper area 3x3 cm and via holes STA339BW powersso-36
package mechanical data STA339BW 74/77 doc id 15251 rev 5 9 package mechanical data figure 26 shows the package outline and ta bl e 8 5 gives the dimensions of the powersso-36 package with exposed pad (slug) down (epd). in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions an d product status are available at: www.st.com . ecopack ? is an st trademark. table 85. powersso-36 epd dimensions symbol dimensions in mm dimensions in inches min typ max min typ max a 2.15 - 2.47 0.085 - 0.097 a2 2.15 - 2.40 0.085 - 0.094 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g- - 0.10 - - 0.004 h 10.10 - 10.50 0.398 - 0.413 h- - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees l 0.60 - 1.00 0.024 - 0.039 m - 4.30 - - 0.169 - n - - 10 degrees - 10 degrees o - 1.20 - - 0.047 - q - 0.80 - - 0.031 - s - 2.90 - - 0.114 - t - 3.65 - - 0.144 - u - 1.00 - - 0.039 - x 4.10 - 4.70 0.161 - 0.185 y 4.90 - 7.10 0.193 - 0.280
STA339BW package mechanical data doc id 15251 rev 5 75/77 figure 26. powersso-36 epd outline drawing h x 45
revision history STA339BW 76/77 doc id 15251 rev 5 10 revision history table 86. document revision history date revision changes 09-dec-2008 1 initial release 16-feb-2009 2 updated names/descriptions for pins 17-20 in chapter 2 on page 12 added cross reference to i 2 s interface setup in section 3.6: power on/off sequence on page 18 updated text and figure 22: application diagram on page 71 updated section 7.2: pll filter on page 71 01-apr-2009 3 updated y dimension in table 85: powersso-36 epd dimensions on page 74 15-may-2009 4 updated chapter 1 on page 10 to ?8 programmable 28-bit biquads? updated i il and i ih in table 6: electrical specifications - digital section on page 15 updated i lim and i sc in table 7: electrical specifications - power section on page 16 updated register fdrc addresses in section 6.1.5: fault detect recovery bypass on page 29 updated bits 4 and 5 in table 73: status register bits on page 64 . 04-aug-2010 5 updated order code in table 1: device summary on page 1 updated name of chapter 9 on page 74 to package mechanical data
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